The present invention relates to static memory systems, and more particularly to two-terminal semiconductor Quantum Dot comprising static memory cells and arrays thereof, in which said static memory cells at least two stable states can be set by application of at least two different state switching D.C. voltage levels, said stable states being detected by the monitoring of A.C. current flow magnitude response to an applied A.C. voltage.
State of the art computer memory and logic devices are made of Complementary Metal Oxide Semiconductor (CMOS), and four devices are required per memory cell. A typical CMOS cell has a linear dimension of 2500 Angstroms, hence a typical cell volume is 2.5xc3x971011 cubic Angstroms. Thus it takes 1 Billion atoms to make a single static random access (SRAM) cell.
In contrast to CMOS cells, which are based on three terminal devices and are applied in logic circuits with fan-in and fan-out requirements, a present invention cell has only two terminals such that the memory system is functionally similar to that provided by magnetic media in which magnetic dipoles can be set to one of two stable states, and later said state detected.
Known references include a paper titled xe2x80x9cElectronic Bistability In Electrochemically Self-Assembled Quantum Dots: A Potential Nonvolatile Random Access Memoryxe2x80x9d, by Kouklin, Bandyopadhyay, Tereshin, Varfolomeev and Zaretsky, published in Applied Physics Letters, Vol. 76, No. 4, in January of 2000, which was the first publication specifically on present invention quantum state monitoring, although U.S. Pat. No. 5,747,180 to Miller et al. for which Inventor Bandyopadhyay in this Application was co-inventor, describes methodology for making Quantum Dots. Additional Patents identified are:
U.S. Pat. No. 5,923,046 to Tezuka et al., is disclosed as it describes a Quantum Dot Memory Cell in a V-shaped groove. Sensing of current conductance states allows descrimination between a xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d.
U.S. Pat. No. 5,783,840 to Randall et al. is disclosed as it describes a Universal Quantum Dot Logic Cell.
Applied electric potentials allow modulating quantum states, thus controlling electron tunneling through the tunneling barriers.
U.S. Pat. No. 5,959,896 to Forbes describes a multi-state flash memory cell and method of programming single electron differences. Trapped electrons cause change in drain current of a transistor.
Additional references include xe2x80x9cElectrochemically Assembled Quasi-Periodic Quantum Dot Arraysxe2x80x9d, Bandyopadhyay et al., Nanotechnology, Vol. 7 P. 360-371 (1996), which shows a bright field electron microscope micrograph of pores on the order to 10 nm which were formed by annodization of aluminum performed in sulfuric acid.
Another known article, which describes magnetic properties of spatially ordered two-dimensional arrays of quantum dots, is titled xe2x80x9cMagnetic Properties of Fe Deposited into Anodic Aluminum Oxide Pores as a Function of Particle Sizexe2x80x9d, AlMawlawi et al., J. Appl. Phys. 70, 4421 (1991).
An article which describes non-linear optical properties of spatially ordered two-dimensional arrays of quantum dots, is xe2x80x9cIntrinsic Optical Non-linearity and Secoind Harmonic Generation in Electrochemically Self-Assembled CdS Quantum Dotsxe2x80x9d, Balandin et al., Phys. Low-Dim. Struct, 11/12, 155 (1997).
An article which discusses tunneling in two terminal switched state devices is xe2x80x9cQuantum Transistors: Toward Nanoelectronicsxe2x80x9d, Editor Linda Geppert, IEEE Spectrum (2000).
Even in view of the cited references, there remains need for improved quantum-dot based, non-volatile two-terminal electronic bistable memory systems, and methods of sensing quantum states therein.
In its most basic sense, the present invention system can be described as comprising, in functional combination:
means for sequentially applying D.C. and A.C. voltages to memory cells which are comprised of quantum dots, said means for applying D.C. and A.C. voltages including means for measuring A.C. current flow; and
a two-terminal static memory cell comprised of Quantum Dots, said two-terminal static memory cell having at least two stable states that can be set by application of at least two different state switching D.C. voltage levels across said two terminals, said stable states being detectable by the monitoring of A.C. current flow magnitude response to an applied A.C. voltage, also applied across said two terminals. Further, a preferred present invention two-terminal static memory cell typically provides that each Quantum Dot therein be comprised of semiconductor and be approximately 10 nm in diameter so as to comprise approximately 1000-10,000 atoms, such that each memory cell has in a volume of approximately 6.4xc3x97107 cubic Angstroms, (which corresponds to about 300,000 atoms), such that each memory cell is comprised of a multiplicity of said Quantum Dots.
The present invention is further, in combination with means for applying D.C. and A.C. voltages to memory cells comprising quantum dots, which means for applying D.C. and A.C. voltages include means for measuring A.C. current flow, an array of such two-terminal static memory cells, each two-terminal static memory cell in said array thereof being comprised of Quantum Dots, wherein for each static memory cell at least two stable states can be set by application of at least two state switching D.C. voltage levels, said stable states being detectable by the monitoring of A.C. current flow magnitude response to an applied A.C. voltage. And again each present invention two-terminal static memory cell typically provides that each Quantum Dot is made of semiconductor and is approximately 10 nm in diameter so as to comprise approximately 1000-10,000 atoms, such that each memory cell has in a volume of approximately 6.4xc3x97107 cubic Angstroms, (which corresponds to about 300,000 atoms), such that each memory cell is comprised of a multiplicity of said Quantum Dots.
Present invention two-terminal static memory cells then enable setting one or another stable state therein by the application of a D.C. voltage level in one of a plurality of ranges across said two terminals thereof. The stable state set is readable, or retrievable by application of an A.C. voltage in combination with monitoring current flow level caused thereby.
Again, while not limiting, for emphasis it is repeated that present invention static memory cells preferably comprise 10 nm dimension semiconductor Quantum Dots and that a present invention static memory cell occupies a volume on the order of 6.xc3x97107 cubic Angstroms, (which corresponds to about 300,000 atoms). This represents a 3000+ times improvement over packing density presently possible in CMOS systems. It is noted that each 10 nm dimension Quantum Dot comprises 1000-10,000 atoms, hence multiple Quantum Dots comprise a single present invention Static Random Access Memory (SRAM) cell. In the context of the recited dimensions it is noted that the operational principal of the present invention is thought to involve tunneling behavior between the Quantum Dots which are semiconductor in nature, which semiconductor Quantum Dots function as carrier traps of more or less efficiency, depending on the state set therein. (It is noted that intial work has utilized CdS as the semiconductor, but that use of any semiconductor is within the scope of the present invention).
A method of the present invention involves providing a present invention static memory cell as described above, then setting it into one or another stable state by the application of a D.C. voltage level in one or another range of D.C. voltages, and then monitoring or retrieving said set stable state by application of an A.C. voltage in combination with monitoring current flow level caused thereby. Of course said method can include resetting the stable state and repeating the described procedure. When an array of said static memory cells are present and each is involved in practice of the method, it should be appreciated that a digital memory function, functionally essentially transparent to that enabled by multiple dipole cell providing magnetic media, is enabled.
It is noted that realized present invention system static memory cells have demonstrated bistable states.
The present invention will be better understood by reference to the Detailed Description Section of this Specification, with reference to the Drawings.
It is therefore a primary objective and/or purpose of the present invention to:
in the context of two-terminal static memory cells made from quantum dots, wherein each quantum dot is approximately 10 nm in dimension so as to comprise approximately 1000-10,000 atoms, and wherein each memory cell has in a volume of approximately 6.4xc3x97107 cubic Angstroms, corresponding to about 300,000 atoms,
teach setting therein, by application of D.C. voltages, and monitoring, by application of A.C. voltages across the two terminals thereof while monitoring resulting A.C. current flow, at least two possible stable states.
It is another objective and/or purpose of the present invention to teach arrays of two-terminal static memory cells made from quantum dots, each being as described in the primary objective and/or purpose.
Other objectives and/or purposes of the present invention will become apparent by reference to the Specification and Claims.